Operating Principles

Table 2-5 describes the functions of the main components on the C204 MAIN and C204 DRV board.

Table 2-5. Main IC Functions


IC Name




TMP95C061 (CPU)


Receives data from the host computer via the gate array, loads the data to the input buffer in the RAM, and converts the image data to print data.



The main features are:

(Gate Array)

• /CS (Chip Select) signal creation

• Address decoding

• Address latching

• Clock pulse creation

• Printhead driver control

• CR motor driver control

• CR and PG motor pulse encoder I/O (input/output)

• Phase signal creation for the motors

• Interface control

• Abnormal CR and PF motor detection

• /RESET signal creation



Contains the program that runs the CPU.



Holds the CPU working area and buffers (input,, line,, and image buffers).



Memorizes the printer unique parameter during the power is off.



EIA to Logic level voltage level converter



System reset IC

C204 DRV



Drives the CR motor.



Drives the PF motor.



Detects the current in the CR motor driver and feeds it back to the gate array on the C204 MAIN board.

Figure 2-16 shows the data flow for data input via the parallel interface. Although various circuits perform data processing, the control core is the CPU and all operations are executed via the CPU. In this circuit, the

E05B36 IC (IC1) provides the interface between the external host computer and the CPU, and all data processing is performed by read/write operations to MMIO (Memory Mapped Input / Output).

Data from the host computer is latched by repeating steps 1 through 3 below.

1. Upon receiving the /STROBE pulse, IC1 latches the data into ports PDATA 1 - 8 and sets the BUSY signal to HIGH.

2. The CPU reads the latched data from the MMIO port, checks whether the data is a print command (CR code), and stores it in the input data buffer if it is not.

3. After checking the data, the CPU makes IC1 clear the BUSY signal and output the /ACKNLG signal, via the MMIO accesses. When either a CR code is received or the input data buffer becomes full, the CPU sets the BUSY signal to HIGH and executes printing.

4. The CPU reads the data from the input data buffer, analyzes each byte to determine whether it is a character or a command, and converts it to print data. The print data consists of 1-byte character codes and 2-byte attributes. Character data is stored as character codes and commands or character types are stored as attributes.

5. The print data is stored in the line buffer in units of one line of data.

6. The CPU reads the print data stored in the line buffer byte by byte, accesses the CG (Character Generator), and expands the data in the image buffer (in the case of download characters, in the download CG). A row of expanded data is output to the printhead control circuit as printhead data.

Note : The data flow from the Type-B I/F card is the same as the data flow from the parallel interface, described above, except the signal names and data access method differ.

Figure 2-16. Parallel Interface Data Flow

This section describes the hardware reset circuit. When the hardware reset signal is input, all ICs in the control circuit are reset, and the CPU executes the program from the starting address. Figure 2-17 shows the reset circuit block diagram.

The circuit is equipped with a reset IC: PTS591(IC13) is used for resetting the + 5 VDC line. The reset operation is described below.

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