Control Circuit

Figure 2-14 shows a block diagram of the control circuit, with the main board at20the center. The printer employs a uPD78322 internal 16-bit processing/external 8-bit bus one-chip CPU (5E) as the main CPU. This CPU is driven with a 14.7 MHz external clock (CR2).

The control program is stored in the internal mask ROM (5E: mainly for mechanism 20control) and external PROM 27 (3B: mainly for ESC/P and IBM emulation, interfacing, and CG). The CPU starts executing the program upon receiving the reset signal from an external device.

The internal RAM and the external PSRAM HM6264 are used for memory space. Also, the non-volatile memory circuit is used to store the operating parameters set using the control panel, such as the TEAR OFF position, and the factory adjustment parameters, while the printer power is turned off.

Two gate arrays, E05A38NA (6A) and E05A16GA (2E) are used to allocate the memories20and I/O area, in order to simplify the circuit. Both gate arrays are controlled by the CPU via the address bus using MMIO (Memory Mapped 1/0).

The functions of the primary ICs are as follows:

The /¿PD70322 is the main CPU in the control circuit. It receives parallel datavia gate array (6A) or directly receives serial data (from the host computer) and stores the data in an input buffer in the SRAM (3 B).

When the printing start interrupt routine (the CPU receives the CR code or the input buffer becomes full) is started, the CPU expands the data in the input buffer to the image buffer by accessing the character generator (CG). Then it transfers the image data to the E05A38NA (6A) and sets the head data.

During printing, the CPU outputs the FIRE signal from the internal timer to control print timing. The MMU (Memory Management Unit) in the CPU controls the memories via external devices such as the slave CPU (E05A38NA in this printer).

An internal 8-channel 8-bit A-D converter is used for checking the status of each sensor in the mechanisms, the panel/DIP switch status, and the power supply voltage.

Upon receiving a signal indicating a problem (SO or CL), or the ON LINE signal, the CPU executes physical interrupt processing using the interrupt port.

The E05A38NA is a custom gate array containing the following functions in a single chip.

- Address decoder: Generates the chip select signal.

- Address latching: Latches and outputs the lower address.

- Print data generation: Controls dividing of the data into two halves (for each row of the printhead)

- DC motor driver: Controls the carriage motor.

Controls the printhead cooling fan.

- Pulse counter: Counts pulses from the carriage motor encoder.

- Interface controller: Controls the parallel interface.

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The E05A38NA is controlled by the CPU using ports. The ad dress timing is controlled by connecting the ASTB (Address Latch Strobe) pulse from the CPU to the ALE (Address Latch Enable) terminal.

Although the data read/write timing is controlled by commands from the CPU, the gate array directly controls the printer mechanism and interface once the parameters are set. In particular, the DC motor control section separately controls the printing operation (driving and stopping the motor) using an external oscillator circuit exclusive for this gate array, unless the printing mode is not changed. The status of the internal registers and ports are initialized upon receiving the reset signal.

The E05A16GA is a one-chip gate array common to the | Pr containing the following functions:

- Super/subscript generator: Converts normal character generator lt; e patterns (image data) into super/subscript character data, and outputs it.

- Italic character generator: Converts normal CG patterns (image data) into italic character data and outputs it.

- Reset signal generator: Takes the logical sum of the external reset signals from two lines and outputs it to the external devices.

- Output port with various output formats for different applications:

CR motor control circuit, plunger drive circuit, control panel lamp control circuit, DIP switch status read circuit drive signals, and motor drive signals.

- General-purpose input port: GAP/TRCT/cutter (optional) sensor signal, status of the paral-

lei interface, control panel switch status, PD (Power Down power supply board) signal

- 8-bit parallel interface control: Inputs the PE and ERROR signals.

- Serial interface control: When using the serial interface, this chip multiplexes the two receive data lines (RXD and bit 7 of the 8-bit parallel interface) using internal logic, and out puts the result to an external device.

The E05A 16GA is controlled by the CPU via MM IO. Addressing is performed using the lower three bits (AO to AZ) of the address bus.

The internal registers and ports are initialized upon receiving the reset signal.

POWER SUPPLY

BOARD

-BOPS

-BOPSE

-BOPSE

DRIVER BOARD UNIT

Figure 2-14. Control Circuit Block Diagram

DRIVER BOARD UNIT

Figure 2-14. Control Circuit Block Diagram

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