Figure 2-15 shows a block diagram of the interface circuit.
This section describes the data flow when data is input or output via each interface. • Parallel interface
When the E05A38NA gate array latches the data from the host computer (upon receiving the STRB signal), it automatically outputs the BUSY signal. The CPU reads the software BUSY status by reading an MMIO port, and stores the data in the input buffer. After the CPU checks the data, it causes the E05A38NA to clear the BUSY signal and output the ACK signal to the host computer.
The receive data RXD (RECEIVE DATA) from the host computer and the bit 7 data from the 8-bit parallel interface (when optional serial interface #8 143 is used) are multiplexed using the internal logic of the E05A16GA gate array, and is output to the CPU asynchronous serial communication interface (ASCI).
The data is transferred from the CPU to the input buffer.
The transmit data TXD (TRANSMIT DATA) is output directly from the ASCI in the CPU.
In the case of the DC 1/DC3 protocol, the DC3 code is output when the buffer becomes full. (The
DC 1 code is output when the buffer is ready for more data.)
The REV signal (same as DTR: DATA TERMINAL READY) is output on the same line as the parallel interface BUSY signal, and performs DTR control. Therefore, the parallel and serial interfaces cannot be used at the same time.
Printing is started when the CR code is input or the buffer becomes full. The data in the input buffer is expanded into the line edit buffer, and the image data referenced by each parameter of the line edit buffer is expanded into the image buffer (by accessing the CG). The expanded image data is transferred to the E05A38NA gate array in units of 8 bits, and becomes the print data.
PE/ERROR/AUTO FEED XT/SUN/ INIT SIGNAL
REV RXD TXD SERIAL l/F
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