List Of Tables

Table

A-1.

Table

A-2.

Table

A-3.

Table

A-4.

Table

A-5.

Table

A-6.

Table

A-7.

Table

A-8.

Table

A-9.

Table A-1 O.

Table A-1 1.

Table A-1 2.

Table A-1 3.

Table

A-1 4.

Table A-1 5.

Table A-1 6.

Table A-1 7.

Table

A-18.

Table A-1 9.

Table

A-20.

Table

A-21.

Table

A-22.

Table

A-23.

Table

A-24.

Table

A-25.

Table

A-26.

Table

A-27.

IC List (PEGX Board) A-1

Transistor List A-1

/iPD7810 Mode Setting ,.A-4

fiPD7811PF Operation ,.A-4

ftPD7810PF Operation ,.A-4

mPD781 0/781 1 Port Functions A-5

GA E05A15HA Port Functions A-9

GA E05A15HA Control Functions A-1 1

GA E05A16GA Port Functions A-1 5

GA E05A16GA Control Functions A-1 7

GA E05A16GA Initialized State A-1 8

HM27256 EP-ROM Signal Status A-20

HM6264ALSP-12 Signal Status A-22

STK6722H Terminal Functions A-25

Connector CN1 Pin Assignments A-28

Connector CN2 Pin Assignments A-28

Connector CN3 Pin Assignments A-28

Connector CN4 Pin Assignments A-28

Connector CN5 Pin Assignments A-28

Connector CN6 Pin Assignments A-28

Connector CN7 Pin Assignments A-28

Connector CN8 Pin Assignments A-28

Connector CN9 Pin Assignments A-28

Connector CN1 O Pin Assignments A-28

Connector CN11 Pin Assignments A-28

FX-850 Parts Name Reference A-33

FX-1 050 Parts Name Reference A-37

A.1 IC DESCRIPTIONS

This section describes the primary ICs used in the FX-850/1050.

Table A-1. IC List (PEGX Board)

Name

Description

Part Number

Location

wPD7810HG

Main CPU

X4000780 10

4B

E05A15HA

Gate Array

Y46 1800002

3A

E05A16GA

Gate Array

1800003

7A

HM6264ALSP-15

ST-RAM 64K bit

X400662647

5A, 6 A

STK6722H

Hybrid IC

X4406722 10

2A

NJ M2355

Switching Regulator

X440072350

1A

Table A-2 Transistor List

Transistor Name

I Description

Part Number

Location

2SC3987

60±10V, 3A, 2W

X302398709

Q1-Q9, Q16

2SA1 450

80V,500mA,600mW

X300145009

Q1O, 12

2SC3748

60V, 1 0 A

X302374809

Q11

2SC3746

60V, 5 A

X302374609

Q13

2SB765K

120V, 3 A, 1.5W

X301 076530

Q15

2SB1318

100V, 3A, 1.2W

X301131809

Q17

2SD560 (4)

120V, 5A, 1.5W

X303056009

Q18-Q21

2SC18 15

60V, 150mA, 400mW | X302181589

Q22, Q25, Q30

2SA10 15

50V, 150mA, 400mW | x3 o o1 o 1 5o9

Q23, Q24

The /¿PD78 10/781 1 is an 8-bit CPU and includes two 8 bit timer counters, an 8-bit A/D converter, 256 bytes of RAM, and a serial interface. A system can be easily constructed using this IC.The main features of this IC are as follows.

• 256 bytes built-in RAM (addresses FFOOH-FFFFH)

• 4096 bytes maks ROM (addresses O-FFOOH) for the 7811 CPU

• Direct addressing of up to 64K bytes . 8-bit A/D converter

• 158 instructions

• 16-bit event counter

• Two 8-bit timer counters

• 3 external and 8 internal interrupts; 6 priority levels and 6 interrupt addresses.

• General purpose serial interface (asynchronous, synchronous, and I/O modes)

• I/O line (781 1 :40-bit I/O port; 78 10:24-bit edge detection, 4 inputs)

• Zero corss detection

• Standby function

• Built-in clock pulse circuit

Figures A-1 and A-2 illustrate the 78 10/781 1 HG microprocessor, and Tables A-3 through A-6 describe its functions.

PF 1

AVcc

AN7 AN6 AN5 AN4 AN3 AN2 AN] ANO AV ss

o oo

VAREF O-AVcc O-AVss O-

SERIAL I/O

INT CONTROL

TIMER

timer

IVENT COUNTER

A/D CONVERTER

18 I

LATCH

MAIN

J GR

ALT GR

PROGRAM MEMORY (4K-BYTE) (^07811)

ir e

DATA MEMORY

(256-BYTE)

INTERNAL

DATA

INST REG

INST DECODER

ABI5-8

C~QpA7 0

READ/WRITE CONTROL

SYSTEM CONTROL

STANDBY CONTROL

H

RD WR ALE MODE 1MODE2 RESET Vdo

RD WR ALE MODE 1MODE2 RESET Vdo

Vcc Vss

Table A-3. /¿PD781 O Mode Setting

Mode 1

Mode O

External memory

o

0

4K bytes. Addresses O to OFFF

o

1 (Note)

16K bytes Addresses O to 3FFF

1 (Note)

1 (Note)

64K bytes Addresses O to OFFF

NOTE: Pull-up is made.

NOTE: Pull-up is made.

Table A-4. /xPD781 1 PF Operation

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PFO

External Memory

Port

Port

Port

Port

Port

Port

Port

Port

256 bytes (max.)

Port

Port

Port

AB 11

AB 10

AB9

AB8

4K bytes

Port

Port

AB 13

AB 12

11

AB 10

AB9

AB8

16K bytes (max.)

AB 15

AB 14

AB 13

AB 12

AB 11

AB 10

AB9

AB8

60K bytes (max.)

Table A-5. ¿¿PD781 O PF Operation

MODE 1

MODE O

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PFO

External Memory

o

0

Port

Port

Port

Port

AB 11

AB 10

AB9

AB8

4K bytes max.)

o

1

Port

Port

AB 13

AB12

AB 11

AB 10

AB9

AB8

16K bytes (max.)

1

1

AB 15

AB 14

AB 13

AB 12

AB 11

AB 10

AB9

AB8

64K bytes (max.)

Table A-6. ¿¿PD781 0/781 1 Port Functions

Pin

Sginal

Direction

Descriptions

1-8

pao-7

In/Out

Port A: Eight-bit l/O with output latch. l/O possible by mode A (MA) register. Output HIGH.

9-16

PBO-7

In/Out

Port B: Eight-bit I/O with output latch. I/O possible by mode B (MB) register. Output HIGH.

17-24

pco-7

In/Out

Port C: Eight-bit I/O with output latch. Port/Control mode can be set by mode control C (MCC) register. Output HIGH

25

NMI

In

Non-maskable interrupt of the edge trigger (trailing edge).

26

1

In

Maskable interrupt input of the edge trigger (leading edge). Also used as the AC input zero cross detecting terminal.

27, 29

MODE 1,0

7810 modes set in accordance with external memory (see Table A-2)

28

reset

In

LOW reset

30, 31

X2,X1

Crytal connection for built-in clock pulse. When clock pulses are supplied externally, input must be to X 1.

32

Vss

Supply voltage, Vss, OV

33

AVss

Analong Vss

34-41

ANO-7

In

Eight analog inputs of the A/D converter. AN7-4 can be used as the input terminals to the detect the leading edge and to set the test flag upon detection of the trailing edge.

42

VAref

In

Reference voltage

43

AVcc

Analog Vcc

44

RD

out

Read strobe. LOW at the read machine cycle and at reset, HIGH at other times.

45

WR

out

Write strobe. LOW during the write machine cycle and at reset, HIGH at other times.

46

ale

out

Address latch enable. Latches the lower 8 address bits to access external memory.

47-54

78: 1 1: Port bit-by-bit I/O possible by mode F register. In extension mode gradual address output assignment is possible in accordance with the size of external memory. See Table A-3. 78 10: By setting modes O and 1, assignment to the address bus (AB 15-8) can be made in accordance with the size of the external memory. The remaining terminals can be used as l/O ports. See Table A-4.

55-62

781 1: Port bit-by-bit I/O possible. In extension mode, PD7-0 act as the multiplexed address/data but (AD7-0).

78 10: Multiplexed address/data bus to access external memory.

63

Vdd

Supply voltage, Vdd+5v

64

Vcc

Supply voltage, Vcc +5v

NOTE: "Direction" refers to the direction of signal flow as viewed from the CPU.

NOTE: "Direction" refers to the direction of signal flow as viewed from the CPU.

Refer to Figures A-3 through A-5 for CPU timing diagrams.

Three oscillations define one state. The OP code fetch requires four states; during Tl to T3, program memory is read; instructions are interpreted during T4. Address bus lines 15-8 are output from T1to T4. Address but lines 7-0 (PD7-0) are used in the multiplex mode; the address is latched during T1 at the ALE signal. Since the memory addressed is enabled after disengaging the driver (AD7-0), RD is output from T1-T3, fetched at T3, and processed internally at T4. The ALE and RD signals are executed from T1-T3; the OP code fetch for these two signals is performed at T4. The WR signal is output from the middle of T 1 to the beginning of T3. The address and ALE timing is the same as that for memory read; however following address output AD7-0(PD7-0) are not disabled, and write data is output at AD7-0 at the beginning of T1 and the end of T3.

NOTE: When PD7-0 are set to the multiplexed address/data-bus (AD7-0) to the address bus (AB7-0), the RD and WR signals in the machine cycle are HIGH when memory is not being accessed.

CLOCK

CLOCK

ADDRESS

OP CODE

ADDRESS

OP CODE

Figure A-3. OP Code Fetch Timing

Figure A-3. OP Code Fetch Timing

CLOCK

CLOCK

ADDRESS

ADDRESS

Figure A-4. Memory Read Timing

Figure A-4. Memory Read Timing

CLOCK

CLOCK

ADDRESS

WRITE DATA

WRITE DATA

A.1.2 Gate Array E05A15HA

The E05A 15HA is a custom gate array used for address latching, address decoding, and automatic phase switching between two channels, and to control head data buffering. The features of this gate array are as follows:

• Latches the low-order address for the /xCOM87 series using the ALE signal.

• Since it has two buffers for print data and automatically activates the half-dot protection circuit, it can protect the printhead from damage due to programming mistake or a malfunction.

• Automatically switches the phases of the carriage motor and paper feed motor using the external clock signal.

BNKO

BNK1

Figure A-6. GA E05A15HA Pin Diagram

DBO TO7

J A 13R

DBO TO7

J A 13R

Figure A-7. GA E05A15HA internal Block Diagram

Table A-7 GA E05A15HA Port Functions

Pin No.

Signal Name

Direction

Function

1 2

BNKO BNK1

OUT OUT

Bank Select signal

CS1

OUT

Chip Select signal

i 11

Po

IN

Input Port

15

PFD

OUT

Motor Control Port (Paper Feed Motor)

HD8

OUT

Prlnthead Data Port

24

N.C

25

Vss

Ground

26

PWD

in

Print Drive Pulse

30

CRD

OUT

Motor Control Port (Carriage Motor)

31

CTRGO

OUT

Cartridge output signal

32

Vdd

+ 5V

33

p5

OUT

output Port

34

WR

IN

Write Strobe signal

35

RD

IN

Read Strobe signal

37

Al 3R Al 4R

OUT

Address output signal

38

HD9

OUT

Printhead Data #9

Al 5

IN

Address Input signal

45

A2

OUT

Address output signal

46

ctrg

IN

Cartridge signal (-)

47

rst

IN

Reset input signal

48

Vss

Ground

49

ale

in

Address Latch Enable signal

50

CTRG +

IN

Cartridge signal (+)

Table A-7. GA E05A15HA Port Functions (cent'd)

Pin No.

Signal Name

Direction

Function

51

A3

i

i

OUT

Address output signal

55

A7

56

DBO

i

J

IN/OUT

Input/Output Data Bus

6 0

DB4

61

DB5

i

f

IN

Input Data Bus

63

DB7

64

Vdd

+ 5V

NOTE: "Direction" refers to the direction of signal flow as viewed from the gate array.

NOTE: "Direction" refers to the direction of signal flow as viewed from the gate array.

Table A-8. GA E05A15HA Control Functions

Address

READ/WRITE

Control Functions

READ

None

WRITE

Data is set to the mode register. Bit 7: -Bit 6: Bank 1 Bit 5: Bank O

Bit 4: Carriage motor rotation

Bit 3: Carriage motor phase switching

0 . . . Automatic control Bit 2: Paper feed motor rotation

0 . . . Counterclockwise (Forward) Bit 1: Paper feed motor phase switching

Bit O: Automatic half-dot protection

READ

Read data from PO-P4.

Bit 7-5: Not used

Bit 4:

P4

Bit 3

P3

Bit 2

P2

Bit 1

P1

Bit O

Write data to P5.

Write P5 data to the mode register bit 5.

READ

Clear 1st printhead data buffer.

WRITE

Clear printhead data

9th bit Head Data" bit 7

READ

Clear 2nd printhead data buffer.

WRITE

Set printhead data.

1st-8th bit Head Data bits 7-0

READ

Read paper feed motor phases. Bit 7-4: Not used

A-phase C-phase B-phase D-phase

WRITE

Set paper feed motor phases Bit 7-7: Not used

A-phase C-phase B-phase D-phase

Table A-8. GA E0515HA Control Functions (cent'd)

Adress

READ/WRITE

Control Functions

05H

READ

Read carriage motor phases.

Bit 7-4: Not used

Bit 3: A-phase

Bit 2: C-phase

Bit 1: B-phase

Bit O: D-phase

WRITE

Set carriage motor phases. Bit 7-4: Not used Bit 3: A-phase Bit 2: C-phase Bit 1: B-phase Bit O: D-phase

A.1.3 Gate Array E05A16GA

The E05A 16GA is a custom gate array used to implement the following functions.

• Super/subscript generator converts the normal CG pattern (image data) received from an external device into super/subscript character data.

• Italic character generator converts the normal CG pattern (image data) received from an external device into italic character data.

• 8-bit parallel interface. Automatically latches the data upon receiving the strobe signal, and sets the BUSY signal HIGH. inputs and outputs other control signals.

• When a serial interface is used, multiplexes the two receive data lines (RXD and the seventh bit of the 8-bit parallel interface) using internal logic, and outputs the result to an external device.

• Logically ANDs the two external reset signal inputs using internal logic, and output the result to an external device (one-channel).

• Output ports with different types of output.

• General purpose input port.

• Bi-directional 8 bit data bus.

065 DB6 D87 RXDIN RSTIN1 GND RSTIN2 IN7 IN6 IN5 IN4 IN3 IN2 STRB GND

IN 1 INO

RSTOUT

BUSY

RXDOUT PD1

PDO PAO Vcc

PA 5

PA 1

Figure A-8. GA E05A16GA Pin Diagram

Figure A-9 shows the gate array block diagram and Table A-9 lists the gate array ports function.

RSTIN2

Figure A-9. GA E05A16GA Internal Block Diagram

Table A-9. GA E05A16GA Port Functions

Pin No.

Signal Name

Direction

Function

f 4

DB7

IN/OUT

Multiplex tri-state data bus bit 4-7 The data is output when RD signal is low.

5

RXDIN

IN

RXD signal input port

6

1

IN

Reset signal input No. 1 RSTIN 1 signal is output to RSTOUT signal port.

7

I Vss I

Ground

IN2

IN IN

Reset signal input No.2 RSTIN 2 signal is output to RSTOUT signal port. Parallel data input port

The data from the host computer is latched when the strobe signal is input.

15

STRB

The parallel data from host computer is latched by STRB signal.

18

IN 1 I NO

The data from the host computer is latched when the strobe signal is input.

19

RSTOUT

OUT

Reset signal output port

2G

BUSY

OUT

Busy signal output port

21 I ACK I OUT I Acknowledge signal output port

22

PE

OUT

Paper end signal output port

23

ERR

OUT

Error signal output port

24 27

PCO

OUT

output port

OUT Serial data output port

OUT Serial data output port

29 3G

PD1 PDO

output port

input port

Input port

36 39

out output port

40 47

output port

Ground

Input port

54 56

Address input port (low address bit O-2)

Table A-9. GA E05A16GA Port Functions (cent'd)

Pin No.

Signal name

Direction

Function

57

Cs

IN

Chip select signal

58

RD

IN

Read strobe signal

59

WR

IN

Write strobe signal

63

DB3

IN/OUT

Multiplex tri-state data bus bit 0-3 The data is output when RD signal is low.

64

VDD

IN

+ 5V

N0TE1: "Direction" refers to the direction of signal flow as viewed from the gate array.

This gate array is accessed by READing and WRITEing the memory mapped I/O addresses (MM 10) using the internal address decoder. The MMIO Ports for this gate array are OOH to 07H, accessed by the lower three bits (AO to A2) of the address bus. Table A-1 O shows the operation of the memory mapped I/O addresses.

Table A-10. GA E05A16GA Control Functions

Address

READ/ WRITE

Control Functions

OOH

READ

PA7-0 -*DB7-0 (Read) The data is inverted.

WRITE

DB7-0-*- PB7-0 (Write) The data is inverted.

01 H

READ

IN7-0 -*■ DB7-0 (Read) The data is inverted.

WRITE

DB7-0-*- PC7-0 (Write) The data is inverted except bit 0 and 1.

02H

READ

Read hard-ware BUSY signal (DBO)

When DBO is high, parallel data is latched in gate array.

WRITE

Write interface parameter to interface control port. Bit 7: Print data

O: "1" bit is print data; 1: "O" bit is print data. Bit 6: Acknowledge signal O: inactive state 1: active state Bit 5: Busy signal

O: High level is active state. 1: Low level is active state. Bit 4: Software Busy signal O: Software Busy state. 1: Ready state. Bit 3: ERR signal

O: inactive state. 1: active state. Bit 2: PE signal

O: inactive state. 1: active state. Bit 1: Serial data input selection. 0: IN7. 1 : RX DIN. Bit O: Parallel data latch timing. 0: Rising edge of STRB. 1: Falling edge of STRB.

03H

READ

Read the converted Italic CG data.

The data is shifted at the falling edge of the RD signal.

WRITE

04H

READ

Shift out the MS bit of the 24 bits shift register. MSB24 -»-DB7

The data is shifted at the rising edge fo RD signal.

WRITE

Load shift register. 1st: DB7-0-» Bit 23-16 2nd: DB7-0-* Bit 15-8 3rd: DB7-0-»- Bit 7-0

This gate array logically ANDs the two external reset signal inputs using internal logic, then outputs ^ the result to an external device (one-channel) and resets the ports internally. Table A-1 1 shows the port settings after they are reset.

Table A-1 O. GA E05A16GA Control Functions (cent'd)

05H

read

Read the 9th pin data of the Super/Subscript generator. Interface parameter bit 7 -»-DB7

WRITE

Write the 9th pin data to the Super/Subscript generator. DB7-* 9th pin data of the Super/Subscript generator.

06H

read

Read 8 bits data from the Super/Subscript generator. 8 bits data of the Super/Subscript generator -*■ DB7-0.

WRITE

Write 8 bits data to the Super/Subscript generator. DB7-0 Super/Subscript generator.

07H

read

Read data from the parallel data latch. IN7-0 DB7-0

WRITE

Write data to the Super/Subscript generator and port D. DB 1-2 -»■ PD 1-2

Table A-1 1. GA E05A16GA Initialized State

Port

Setting

Port B (PB7-PB0)

High

port C (PC7-PB2)

Low

(PC1-PC0)

High

Port D (PD 1)

High

(PDO)

Low

Interface control port

Low

(except bit 2)

(o)

Hard-ware BUSY signal

Low (Ready)

A.1.4 HM27256G-25 EP-ROM

This EP-ROM is a ultra-violet erasable and electrically programmable ROM of 32 K-bytes.

Features

• Capacity of 32768 words X 8 bits

• I/O with TTL compatible

Terminal Functions . AO - Al 4 Input address

• OE Output enable

Vpp t

26 Vcc

A 12 2

n Al 4

4 r 3

26 AIS

A 6 4

2S A 8

A 4 S

24 A 9

A4 6

23 A It

>3 7

22 or

a 2 d

21 AIO

A 1 9

2Ô|cË

AO 10

19 or

0 0 11

16 06

D 1 12

17 OS

0 2 13

16 04

GN0 It

15 03

Figure A-10. HM27256G-25 Pin Diagram

Vcc 0-GNO O Vpp O

Address Input AO A14

Data Out put DO ~ D7

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